Google announced on Monday 9 November two new systems for its eighth-generation TPU line-up. The TPU is Google’s own chip for AI computing. TPU 8tx and TPU 8i Max are not new chips, MarkTechPost and The Decoder reported. Google uses the TPU 8t and TPU 8i chips it unveiled in April and changes their packaging, host processors, memory and networking.

Google says this is the first time it has released four TPU systems in the same year.

TPU 8tx protects data during processing

Data is usually encrypted at rest and in transit. When a processor works on the data, it is decrypted in memory. Google says TPU 8tx keeps data and model weights protected and isolated while in use as well. The system is aimed at regulated industries and government.

TPU 8tx pairs the TPU 8t chip with 5th Gen AMD EPYC processors and uses the Boardfly network from TPU 8i. Google said it cuts latency by up to half compared with TPU 8t, and that the protection barely slows computation. Customers can fine-tune and distil models and train them with reinforcement learning on the same system, the company said. Data does not have to move from one cluster to another. The Decoder noted that Nvidia already offers similar confidential computing for its GPUs.

TPU 8i Max combines two chips

TPU 8i Max puts two TPU 8i chips in one package. Compared with TPU 8i, it doubles compute, on-chip SRAM and HBM bandwidth, Google said. HBM is fast memory packaged next to the chip. Twice as many chips fit in the same rack space. Google is offering the system for AI agents that work through entire codebases or hours of video.

MarkTechPost doubled TPU 8i’s published figures and arrived at about 20.2 petaflops at FP4 precision and about 17.2 TB/s of memory bandwidth per package. Google did not publish these figures or the amount of HBM, although The Decoder writes that memory doubles.

Google gave no availability dates or prices. MarkTechPost cites a Bloomberg report that both systems will become available in 2027.

TPU Sync speeds up cache transfers

Google also released TPU Sync, an open-source C++ library. A language model stores intermediate results for text it has already processed in a KV cache so that it does not have to recompute them. TPU Sync moves this cache between chip memory, server main memory and other TPU nodes.

MarkTechPost summarised Google’s own measurements. In them, median cache transfer latency for the Qwen3 235B model fell from several seconds to about 230 milliseconds. First-token latency fell by an average of 60 per cent on the 235B model and 90 per cent on the 480B model when there were few concurrent requests. The measurements were run on Ironwood chips (TPU v7x), not on the new systems.

Its GitHub page says TPU Sync is tested and optimised for TPU v7x and v6e chips and that its APIs are still changing quickly. PyPI has only development releases so far. The project’s former package names, tpu-raiden-jax and tpu-raiden-torch, are not under its control and should not be installed.